HD6417750 Datasheet, PDF (711/1039 Pages) Renesas Technology Corp – SuperH RISC engine

16.1.2 Block Diagram
Figure 16.1 shows a block diagram of the SCIF.
Module data bus
RxD2
SCFRDR2
(16-stage)
SCRSR2
TxD2
SCK2
SCFTDR2
(16-stage)
SCTSR2
SCSMR2
SCLSR2
SCFDR2
SCFCR2
SCFSR2
SCSCR2
SCSPTR2
SCBRR2
Baud rate
generator
Transmission/
reception
control
Parity generation
Clock
Parity check
External clock
SCIF
SCRSR2: Receive shift register
SCFRDR2: Receive FIFO data register
SCTSR2: Transmit shift register
SCFTDR2: Transmit FIFO data register
SCSMR2: Serial mode register
SCSCR2: Serial control register
SCFSR2: Serial status register
SCBRR2: Bit rate register
SCSPTR2: Serial port register
SCFCR2: FIFO control register
SCFDR2: FIFO data count register
SCLSR2: Line status register
Figure 16.1 Block Diagram of SCIF
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
BRI
Rev. 6.0, 07/02, page 659 of 986