HD6417750 Datasheet, PDF (381/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an
MPX interface is set. This bit is initialized by a power-on reset.
Bit 20: A4MBC
0
1
Description
Area 4 SRAM is set to normal mode
Area 4 SRAM is set to byte control mode
(Initial value)
Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted.
BREQEN is initialized to the external request acceptance disabled state by a power-on reset. It is
ignored in the case of a slave mode startup.
Bit 19: BREQEN
0
1
Description
External requests are not accepted
External requests are accepted
(Initial value)
Bit 18—Partial-Sharing Bit (PSHR): Sets partial-sharing mode. PSHR is valid only in the case
of a master mode startup.
Bit 18: PSHR
0
1
Description
Master mode
Partial-sharing mode
(Initial value)
Bit 17—Area 1 to 6 MPX Interface Specification (MEMMPX): Sets the MPX interface when
areas 1 to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a
power-on reset.
Bit 17: MEMMPX
0
1
Description
SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are
set as SRAM interface (or burst ROM interface)
(Initial value)
MPX interface is selected when areas 1 to 6 are set as SRAM interface (or
burst ROM interface)
Rev. 6.0, 07/02, page 329 of 986