SAM4L Datasheet, PDF (994/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
(CR.DIS). Another way to reset ADCIFE is to write a one in the SWRST field of the Control Reg-
ister (CR.SWRST). In both cases configuration registers won’t be affected.
38.6.9
Analog Reference
Refer to Section 42. ”Electrical Characteristics” on page 1106.
The ADC allows the possibility to select several voltage reference (Vref).
• An internal 1.0V voltage reference derived from the internal 1.1V
• 0.625*Vcc (to get 1.0V when Vcc=1.6V)
• Vcc/2
• 2 external reference inputs
38.6.10 GAIN
The ADC cell allows to affect different gain for each conversion by configuring approprietely the
Gain Factor field GAIN in the SEQCFG register.
The programmable input amplification is from 1x to 64x. Moreover, this amplification can be
divided by 2 by setting all bits in the field GAIN in the SEQCFG register to seven.
38.6.11
Conversion Results
If the Half Word Left Adjust (HWLA) bit in the SEQCFG register is set, then the result will be left
adjusted on the 16 lower bits of the LCV register. Otherwise, results will be right-adjusted.
Positive and negative channels used in the last conversion are available both by reading the
Sequencer Last Converted Value register (LCV).
38.6.12 Operating Modes Overview
Table 38-2. Operating modes description
Operating mode Input range
Output code range
Conversion time Output decimal code
Differential
mode without
gain
-Vref to + Vref
0 to 4095 (11 bits signed 6 clock_cycles
number)
2047 + (Vin/Vref)*2047
Differential
mode with
gain=2n
-Vref/2ⁿ to
+Vref/2ⁿ
0 to 4095 (11 bits signed 7 clock_cycles for 2047 + (2ⁿ*Vin/Vref)*2047
number)
n=1 (gain=2)
9 clock_cycles for
n=6 (gain=64)
Differential
mode with divi-
sion by 2
-2*Vref to
+2*Vref
0 to 4095 (11 bits signed 7 clock_cycles
number)
2047 + (Vin/(2*Vref))*2047
Differential
mode with zoom
and gain =2n
(n>0)
-Vref/2n+Vshift,
Vref/2n+Vshift
Vshift=Vsup(1/4*
zoom-
range[1]+1/8*zo
omrange[0])
0 to 4095 (11 bits signed
number)
7 clock_cycles for
n=1 (gain=2)
10 clock_cycles
for n=6 (gain=64)
2047+(2ⁿ*(Vin-
Vshift)/Vref*2047
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