SAM4L Datasheet, PDF (588/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 24-21. Elementary Time Unit (ETU)
ISO7816 Clock
on CLK
ISO7816 I/O Line
on TXD
FI_DI_RATIO
ISO7816 Clock Cycles
1 ETU
24.6.8.3
Protocol T=0
In T=0 protocol, a character is made up of one start bit, eight data bits, one parity bit, and a two
bit period guard time. During the guard time, the line will be high if the receiver does not signal a
parity error, as shown in Figure 24-22. The receiver signals a parity error, aka non-acknowledge
(NACK), by pulling the line low for a bit period within the guard time, resulting in the total charac-
ter length being incremented by one, see Figure 24-23. The USART will not load data to RHR if
it detects a parity error, and will set PARE if it receives a NACK.
Figure 24-22. T=0 Protocol without Parity Error
Baud Rate
Clock
RXD
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next
Bit
Bit Time 1 Time 2 Start
Bit
Figure 24-23. T=0 Protocol with Parity Error
Baud Rate
Clock
I/O
Error
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard
Bit
Bit Time 1
Guard Start D0 D1
Time 2 Bit
Repetition
24.6.8.4
24.6.8.5
24.6.8.6
Protocol T=1
In T=1 protocol, the character resembles an asynchronous format with only one stop bit. The
parity is generated when transmitting and checked when receiving. Parity errors set PARE.
Receive Error Counter
The USART receiver keeps count of up to 255 errors in the Number Of Errors field in the Num-
ber of Error Register (NER.NB_ERRORS). Reading NER automatically clears NB_ERRORS.
Receive NACK Inhibit
The USART can be configured to ignore parity errors by writing a one to the Inhibit Non
Acknowledge bit (MR.INACK). Erroneous characters will be treated as if they were ok, not gen-
erating a NACK, loaded to RHR, and raising RXRDY.
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