SAM4L Datasheet, PDF (577/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Interrupt Mask Register (IMR.RXRDY) is set. If CSR.RXRDY is already set, RHR will be over-
written and the Overrun Error bit (CSR.OVRE) is set. An interrupt request is generated if the
Overrun Error bit in IMR is set. Reading RHR will clear CSR.RXRDY, and writing a one to the
Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE. Refer to Figure 24-
7.
24.6.3 Other Considerations
24.6.3.1 Parity
The USART supports five parity modes, selected by MR.PAR:
• Even parity
• Odd parity
• Parity forced to zero (space)
• Parity forced to one (mark)
• No parity
The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 578. If even par-
ity is selected (MR.PAR is 0x0), the parity bit will be zero if there is an even number of ones in
the data character, and one if there is an odd number. For odd parity the reverse applies. If
space or mark parity is chosen (MR.PAR is 0x2 or 0x3, respectively), the parity bit will always be
a zero or one, respectively. See Table 24-4.
Table 24-4. Parity Bit Examples
Alphanum
Character
A
V
R
Hex
0x41
0x56
0x52
Bin
0100 0001
0101 0110
0101 0010
Odd
1
1
0
Parity Mode
Even
Mark
0
1
0
1
1
1
Space
0
0
0
None
-
-
-
The receiver will report parity errors in CSR.PARE, unless parity is disabled. An interrupt request
is generated if the PARE bit in the Interrupt Mask Register is set (IMR.PARE). Writing a one to
CR.RSTSTA will clear CSR.PARE. See Figure 24-8.
Figure 24-8. Parity Error
Baud Rate
Clock
RXD
Write
CR
PARE
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Bad Stop
Parity Bit
Bit
RSTSTA = 1
RXRDY
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