SAM4L Datasheet, PDF (202/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
13.6.3.5
in open loop mode is to first configure it for closed loop mode, see Section 13.6.3.5. When a lock
is achieved, read back the COARSE and FINE values and switch to open loop mode using these
values. An alternative approach is to use the Frequency Meter (FREQM) to monitor the DFLL
frequency and adjust the COARSE and FINE values based on measurement results form the
FREQM. Refer to the FREQM chapter for more information on how to use it. Note that the output
frequency of the DFLL will drift when in open loop mode due to temperature and voltage
changes. Refer to Section 42. ”Electrical Characteristics” on page 1106 for details.
Closed Loop Operation
DFLLx must be correctly configured before closed loop operation can be enabled. After enabling
DFLLx, the DFLLx must be configured in the following way:
1. Enable and select a reference clock (CLK_DFLLx_REF). CLK_DFLLx_REF is a
generic clock, refer to Generic Clocks section for details.
2. Write an appropriate value to DFLLxCONF.RANGE to choose desired range of the out-
put frequency.
3. Select the multiplication factor in the Multiply Factor field in the DFLLx Multiplier Regis-
ter (DFLLxMUL.MUL). Care must be taken when choosing MUL so the output
frequency does not exceed the maximum frequency of the device.
4. Select the maximum step size allowed in finding the COARSE and FINE values by writ-
ing the appropriate values to the Coarse Maximum Step field and Fine Maximum Step
field in the DFLLx Maximum Step Register (DFLLxSTEP.CSTEP and DFLLx-
STEP.FSTEP). A small step size will ensure low overshoot on the output frequency, but
can typically result in longer lock times. A high value might give a big overshoot, but can
typically give faster locking. DFLLxSTEP.CSTEP and DFLLxSTEP.FSTEP must not be
higher than 50% of the maximum value of DFLLxVAL.COARSE and DFLLxVAL.FINE
respectively.
5. Optional: Select start values for COARSE and FINE by writing the appropriate values to
DFLLxVAL.COARSE and DFLLxVAL.FINE respectively. Selecting values for COARSE
and FINE that are close to the final values and small step sizes for CSTEP and FSTEP
will reduce the time required to achieving lock on COARSE and FINE. If this step is
skipped, COARSE will start at its current value and FINE will start at half its maximum
value.
6. Start the closed loop mode by writing a one to Mode Selection bit in DFLLxCONF
(DFLLxCONF.MODE).
The frequency of CLK_DFLLx (f_{CLK_DFLLx}) is given by:
f_{CLK_DFLLx} = DFLLxMUL.MUL ⋅ f_{CLK_DFLLx_REF}
where f_{CLK_DFLLx_REF} is the frequency of the reference clock (CLK_DFLLx_REF). DFLLx-
VAL.COARSE and DFLLxVAL.FINE are read-only in closed loop mode, and are controlled by
the frequency tuner shown in Figure 13-3 to meet user specified frequency.
In closed loop mode, the value in DFLLxVAL.COARSE is used by the frequency tuner as a start-
ing point for COARSE and half the maximum value of FINE will be used as a starting point for
FINE. Writing DFLLxVAL.COARSE to a value close to the final value before entering closed loop
mode will reduce the time needed to get a lock on COARSE. This can be done both before or
after writing the multiplication value to DFLLxMUL.MUL. If this is done after writing DFLLx-
MUL.MUL, the value written to DFLLxVAL.FINE will also be used as a starting point for FINE
instead of the default behavior which is to use half the maximum value of FINE.
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