SAM4L Datasheet, PDF (709/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 27-8. Master Read with One Data Byte
TWD S DADR R A DATA
NP
SR.IDLE
RXRDY
Write START &
STOP bit
NBYTES set to 1
Figure 27-9. Master Read with Multiple Data Bytes
TWD S DADR R A
DATAn
Read RHR
A DATAn+1 DATAn+m-1 A
DATAn+m N P
SR.IDLE
RXRDY
Write START +
STOP bit
NBYTES set to m
Read RHR
DATAn
Read RHR
DATAn+m-2
Read RHR
DATAn+m-1
Read RHR
DATAn+m
Send STOP
When NBYTES=0
27.8.5
Using the Peripheral DMA Controller
The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set
up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space
to place received data.
To assure correct behavior, respect the following programming sequences:
27.8.5.1
Data Transmit with the Peripheral DMA Controller
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to transmit.
4. Wait for the Peripheral DMA Controller end-of-transmit flag.
5. Disable the Peripheral DMA Controller.
27.8.5.2
Data Receive with the Peripheral DMA Controller
1. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to receive.
4. Wait for the Peripheral DMA Controller end-of-receive flag.
5. Disable the Peripheral DMA Controller.
42023C–SAM–02/2013
709