SAM4L Datasheet, PDF (746/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one.
See Figure 28-7 and Figure 28-8.
Figure 28-7. Slave Transmitter with One Data Byte
TWD S
DADR
R
A
DATA
N
P
TCOMP
TXRDY
Write THR (DATA)
NBYTES set to 1
Figure 28-8. Slave Transmitter with Multiple Data Bytes
TWD S
DADR
R
A
DATA n
A
TCOMP
STOP sent by master
DATA n+5
A
DATA n+m N
P
TXRDY
Write THR (Data n)
NBYTES set to m
Write THR (Data n+1)
Write THR (Data n+m)
Last data sent
Figure 28-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF
TWD DATA (LSB)
N
P
STOP sent by master
TWCK
SR.NAK
SR.BTF
t₁
t₁
t₁: (CLK_TWIS period) x 2
28.8.5
Slave Receiver Mode
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is
cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one
CLK_TWIS cycle after the relevant address match bit in the same register is set).
After the address phase, the following is repeated:
42023C–SAM–02/2013
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