SAM4L Datasheet, PDF (871/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
32. Audio Bit Stream DAC (ABDACB)
Rev: 1.0.0.0
32.1 Features
• 16 bit digital stereo DAC
• Oversampling D/A conversion architecture
– Adjustable oversampling ratio
– 3rd order Sigma-Delta D/A converters
• Digital bitstream output
• Parallel interface
• Connects to DMA for background transfer without CPU intervention
• Supported sampling frequencies
– 8000Hz, 11025Hz, 12000Hz, 16000Hz, 22050Hz, 24000Hz, 32000Hz, 44100Hz, and 48000Hz
• Supported data formats
– 32-, 24-, 20-, 18-, 16-, and 8-bit stereo format
– 16- and 8-bit compact stereo format, with left and right sample packed in the same word to
reduce data transfers
• Common mode offset control
• Volume control
32.2 Overview
The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with
an average value proportional to the sample value. Two channels are supported making the
Audio Bitstream DAC particularly suitable for stereo audio. Each channel has a pair of comple-
mentary digital outputs, DAC and DACN, which can be connected to an external high input
impedance amplifier.
The Audio Bitstream DAC is made up of several signal processing blocks and a 3rd order Sigma
Delta D/A converter for each channel. The Sigma Delta modulator converts the parallel data to a
bitstream, while the signal processing blocks perform volume control, offset control, upsampling,
and filtering to compensate for the upsampling process. The upsampling is performed by a Cas-
caded Integrator-Comb (CIC) filter, and the compensation filter is a Finite Impulse Response
(FIR) CIC compensation filter.
32.3 Block Diagram
Figure 32-1. ABDACB Block Diagram
clk_abdacb
gclk
Signal processing
(before up-sampling)
Clock
divider
CLK
Sigma Delta
M odula tor
Sigma Delta
M odula tor
D A C [0 ]
DACN[0]
DAC[1]
DACN[1]
42023C–SAM–02/2013
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