SAM4L Datasheet, PDF (1068/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
An overrun condition is detected if RHR is not read before internal buffer is full. Data in RHR is
corrupted and Overrun bit is set to one in the Status Register (SR.OVR).
40.6.2
Peripheral DMA
PARC can be associated to a Peripheral DMA Controller (PDCA) channel. It will then perform
data transfer from PARC to a memory buffer without any CPU intervention (see PDCA chapter
for channel configuration). PDCA and PARC data size must be equal, if CFG.DSIZE is 32-bit
PDCA must be configured to read 32-bit data size.
PARC requests data transfer when internal buffer is full. When data capture is disabled (with
CR.STOP), PARC requests a last data transfer if internal buffer contains at least one byte.
40.6.3
Peripheral Events
Data capture can be enabled or disabled by peripheral events if Event Mode is enabled
(CFG.EMODE). Start event enables the data capture whereas stop event disables it.
40.6.4
Interrupt Generation
PARC has two interrupt sources, Data Ready (DRDY) and Overrun (OVR). The status of each
interrupt source can be read from the Status Register. An interrupt request will be generated if a
bit in SR and the corresponding bit in the Interrupt Mask Register (IMR) are set. Bits in IMR are
set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared
by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt
request remains active until the corresponding bit in SR is cleared by writing a one to the corre-
sponding bit in the Interrupt Status Clear Register (ICR).
The interrupt sources are ORed together to make one interrupt request which remains active
until all interrupt bits in SR are cleared.
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