SAM4L Datasheet, PDF (1155/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Table 42-62. JTAG Timings⁽¹⁾
Symbol
Parameter
JTAG0
TCK Low Half-period
JTAG1
TCK High Half-period
JTAG2
TCK Period
JTAG3
TDI, TMS Setup before TCK High
JTAG4
TDI, TMS Hold after TCK High
JTAG5
TDO Hold Time
JTAG6
TCK Low to TDO Valid
JTAG7
Boundary Scan Inputs Setup Time
JTAG8
Boundary Scan Inputs Hold Time
JTAG9
Boundary Scan Outputs Hold Time
JTAG10
TCK to Boundary Scan Outputs Valid
Conditions
Min
21.8
8.6
30.3
2.0
V_VDDIO from
3.0V to 3.6V,
2.3
maximum
external
9.5
capacitor =
40 pF
0.6
6.9
9.3
Max
21.8
32.2
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
42.9.6 SWD Timing
Figure 42-18. SWD Interface Signals
Read Cycle
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Stop
Park
Tos
Tri State
Thigh
Tlow
Tri State
Acknowledge
Data
Data
Tri State
Write Cycle
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Stop
Park
Tri State
Tri State
Tis
Tih
Acknowledge
Data
Data
Parity
Units
ns
Parity
Start
Start
Tri State
42023C–SAM–02/2013
1155