SAM4L Datasheet, PDF (704/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
27.8.2.1
High-speed-mode
After reset and initialization, the TWIM is in Standard-mode, Fast-mode, or Fast-mode Plus (col-
lectively referred to as the F/S-mode). For the TWIM to enter High-speed-mode (HS-mode), the
user must write a one to the HS-mode (HS) bit and write a unique 3-bit code to the HS-mode
Master Code field (HSMCODE) in the Command Register (CMDR) or/and the Next Command
Register (NCMDR). This instructs the TWIM to initiate a HS-mode transfer, when the bus is free,
by transmitting (in F/S-mode) the START condition followed by a unique 8-bit HS-mode master
code (0x00001XXX), which is formed by prefixing CMDR.HSMCODE with 0b00001. This is then
followed by the not-acknowledge bit (NA) on the bus, after which HS-mode transfer commences.
In summary, the conditions for initiating HS-mode transfer are:
1. START condition (S)
2. 8-bit master code (0000 1XXX)
3. Not-acknowledge bit (NA)
HS-mode master codes are reserved 8-bit codes and serve two purposes:
1. It allows arbitration and synchronization between competing masters at F/S-mode
speeds, resulting in one winning master.
2. It indicates the beginning of an HS-mode transfer.
If the TWIM remains as the active master after the transmission of the master code and the NA
bit, it releases the TWCK line and waits for the line to be pulled up to HIGH, during which it does
the following:
1. Adapt the TWD and TWCK input filters to the spike suppression requirement in HS-
mode.
2. Adapt the TWD and TWCK output stages to the slope control requirements in HS-
mode.
Once the TWCK line is HIGH, the TWIM operates in HS-mode and only switches back to F/S-
mode after a STOP condition. If an acknowledge bit (A) is erroneously placed on the bus after
the transmission of the master code, the TWIM sets the HSMCACK bit in the Status Register
(SR) and transmits the STOP condition on the bus.
With regard to the slope control of the TWD and TWCK outputs, the user can control the rise and
fall times of the TWCK output in F/S- and HS-mode by writing the Clock Drive Strength
HIGH/LOW (CLDRIVEH/L) and Clock Slew Limit (CLSLEW) fields of the Slew Rate Register
(SRR) and HS-mode Slew Rate Register (HSSRR), respectively. Likewise, the fall times of the
TWD output in F/S- and HS-mode can be controlled by writing the Data Drive Strength LOW
(DADRIVEL) and Data Slew Limit (DASLEW) fields of SRR and HSSRR, respectively. Refer to
Section 42. ”Electrical Characteristics” on page 1106 for appropriates values of these register
fields.
Note that the fall times of the TWD output are also controlled by the corresponding register fields
in the Two-wire Slave Interface (TWIS) module. In order to correctly control the slew rate of the
TWD output, the user must either
1. Write the relevant register fields in the TWIM with appropriate values and leave those in
TWIS as zeros, or vice versa; or
2. Write the relevant register fields in both the TWIM and the TWIS with the same values.
During HS-mode transfer, the TWIM enables and controls a current-source pull-up circuit at the
output stage of its TWCK signal (if it is the active master) to shorten the rise time of the signal.
The current-source pull-up circuit is temporarily disabled by the TWIM after a REPEATED
START condition and after each acknowledge bit (A) and not-acknowledge bit (NA), thus
enabling other devices connected to the bus to delay the serial transfer by stretching the LOW
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