SAM4L Datasheet, PDF (102/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
10. Power Manager (PM)
Rev: 4.4.1.1
10.1 Features
• Generates clocks and resets for digital logic
• On-the-fly frequency change of CPU, HSB and PBx clocks
• Module-level clock gating through maskable peripheral clocks
• Controls resets of the device
10.2 Overview
The Power Manager (PM) provides synchronous clocks used to clock the main digital logic in the
device, namely the CPU, and the modules and peripherals connected to the High Speed Bus
(AHB) and the Peripheral Buses (APBx).
The synchronous clocks are divided into a number of clock domains, one for the CPU and AHB
and one for each APBx. The clocks can run at different speeds, so the user can save power by
running peripherals at a relatively low clock, while maintaining a high CPU performance. Addi-
tionally, the clocks can be independently changed on-the-fly, without halting any peripherals.
This enables the user to adjust the speed of the CPU and memories to the dynamic load of the
application, without disturbing or re-configuring active peripherals. Each module also has a sep-
arate clock, enabling the user to switch off the clock for inactive modules, to save further power.
Additionally, clocks and oscillators can be automatically switched off during Power Save Mode
periods by using the Power Save Mode feature of the Backup Power Manager module (BPM).
The Power Manager also contains a Reset Controller, which collects all possible reset sources,
generates hard and soft resets, and allows the reset source to be identified by software.
10.3 Block Diagram
Figure 10-1. PM Block Diagram
SCIF/
BSCIF
BPM
Main Clock Sources
Power Save Mode
Synchronous Clock
Generator
Synchronous
clocks
CPU, AHB,
APBx
NVIC
User Interface
APB Bus
Reset Sources
External Reset Pin
Reset Controller
resets
PM
42023C–SAM–02/2013
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