SAM4L Datasheet, PDF (423/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Finally, AESA supports several hardware countermeasures that are useful for protecting data
against differential power analysis attacks (Section 18.4.5 on page 427).
Figure 18-1. AESA Block Diagram
DMA
Controller
Hardware
Handshaking
Interface
CLK_HSB
DMA Controller
High Speed Bus
High Speed Bus
Slave
CLK_AESA
IRQ
Core
AESA
Interrupt
Controller
18.3
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
18.3.1
Power Management
If the CPU enters a sleep mode that disables clocks used by AESA, the module will stop func-
tioning and resume operation after the system wakes up from sleep mode.
18.3.2 Clocks
The clock (CLK_AESA) for AESA’s core operations (such as encryption and decryption) is a
generic clock (GCLK). It is recommended that AESA be disabled before CLK_AESA is disabled
to avoid freezing the module in an undefined state.
18.3.3 Interrupts
The AESA interrupt request line is connected to the NVIC. Using the AESA interrupt requires the
NVIC to be programmed first.
18.4 Functional Description
18.4.1
Basic Programming and Operation
AESA must be enabled before it can be programmed or used. It is enabled by writing a one to
the Enable Module (ENABLE) bit in the Control (CTRL) register. The module is disabled by writ-
ing a zero to the same bit.
AESA supports both the encryption and decryption of data. The desired mode of data process-
ing is selected by programming the Encryption (ENCRYPT) bit in the MODE register.
The 128-bit key is written to the four 32-bit KEY registers. Note that access to the KEY registers
is by 32-bit words only (i.e., no halfword or byte access).
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