SAM4L Datasheet, PDF (496/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
21.4 I/O Lines Description
Table 21-1.
Pin Name
NMI
EXTINTn
I/O Lines Description
Pin Description
Non-Maskable Interrupt
External Interrupt
Type
Input
Input
21.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
21.5.1 I/O Lines
The external interrupt pins (EXTINTn and NMI) may be multiplexed with I/O Controller lines. The
programmer must first program the I/O Controller to assign the desired EIC pins to their periph-
eral function. If I/O lines of the EIC are not used by the application, they can be used for other
purposes by the I/O Controller.
It is only required to enable the EIC inputs actually in use. If an application requires two external
interrupts, then only two I/O lines will be assigned to EIC inputs.
21.5.2
Power Management
All interrupts are available in all sleep modes as long as the EIC module is powered. However, in
sleep modes where CLK_SYNC is stopped, the interrupt must be configured to asynchronous
mode.
21.5.3 Clocks
The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager.
The filter and synchronous edge/level detector runs on a clock which is stopped in any of the
sleep modes where the system RC oscillator (RCSYS) is not running. This clock is referred to as
CLK_SYNC.
21.5.4
21.5.5
Interrupts
The external interrupt request lines are connected to the NVIC. Using the external interrupts
requires the NVIC to be programmed first.
Using the Non-Maskable Interrupt does not require the NVIC to be programmed.
Debug Operation
When an external debugger forces the CPU into debug mode, the EIC continues normal opera-
tion. If the EIC is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.
21.6 Functional Description
21.6.1
External Interrupts
The external interrupts are not enabled by default, allowing the proper interrupt vectors to be set
up by the CPU before the interrupts are enabled.
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