SAM4L Datasheet, PDF (345/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
• The control and status fields for the endpoint and bank (EPn_CTR_STA_BK0/1):
Table 17-4. EPn_CTR_STA_BK0/1 structure
31:19
-
18
17
Status elements
UNDERF OVERF
16
CRCERR
15:1
-
0
Control elements
STALLRQ_NEXT
– UNDERF: Underflow status for isochronous IN transfer. See ”Data flow error” on
page 352.
– OVERF: Overflow status for isochronous OUT transfer. See ”Data flow error” on
page 352.
– CRCERR: CRC error status for isochronous OUT transfer. See ”CRC error” on page
352.
– STALLRQ_NEXT: Stall request for the next transfer. See ”STALL request” on page
345.
17.6.2.12
STALL request
For each endpoint, the STALL management is performed using:
• The STALL Request (STALLRQ) bit in UECONn is set to initiate a STALL request.
• The STALLed Interrupt (STALLEDI) bit in UESTAn is set when a STALL handshake has been
sent.
To answer requests with a STALL handshake, STALLRQ has to be set by writing a one to the
STALL Request Set (STALLRQS) bit. All following requests will be discarded (RXOUTI, etc. will
not be set) and handshaked with a STALL until the STALLRQ bit is cleared, by receiving a new
SETUP packet (for control endpoints) or by writing a one to the STALL Request Clear (STALL-
RQC) bit.
Each time a STALL handshake is sent, the STALLEDI bit is set by the USBC and the EPnINT
interrupt is set.
The user can use the descriptor to manage STALL requests. The USBC controller reads the
EPn_CTR_STA_BK0/1.STALLRQ_NEXT bit after successful transactions and if it is one the
USBC controller will set UECON.STALLRQ. The STALL_NEXT bit will be cleared upon receiving
a SETUP transaction and the USBC controller will then clear the STALLRQ bit.
• Special considerations for control endpoints
If a SETUP packet is received at a control endpoint where a STALL request is active, the
Received SETUP Interrupt (RXSTPI) bit in UESTAn is set, and the STALLRQ and STALLEDI
bits are cleared. It allows the SETUP to be always ACKed as required by the USB standard.
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the user requests a STALL and can return to the main task, waiting
for the next SETUP request.
• STALL handshake and retry mechanism
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ bit is set and if there is no retry required.
42023C–SAM–02/2013
345