SAM4L Datasheet, PDF (310/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
15.6
Module Configuration
The specific configuration for each HMATRIX instance is listed in the following tables.The mod-
ule bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power
Manager (PM)” on page 102 for details.
Table 15-3. HMATRIX Clocks
Clock Name
Description
CLK_HMATRIX
Clock for the HMATRIX bus interface
15.6.1
Bus Matrix Connections
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU IDCODE master interface.
Table 15-4.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
High Speed Bus Masters
CPU IDCODE
CPU SYS
SMAP
PDCA
USBC
CRCCU
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, SCFG5 is
associated with the Internal SRAM Slave Interface.
Accesses to unused areas returns an error result to the master requesting such an access.
Table 15-5.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
High Speed Bus Slaves
Internal Flash
AHB-APB Bridge A
AHB-APB Bridge B
AHB-APB Bridge C
AHB-APB Bridge D
Internal SRAM
Internal SRAM for cache
AESA
42023C–SAM–02/2013
310