SAM4L Datasheet, PDF (602/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 24-39. Master Node with Peripheral DMA Controller (LINMR.PDCM=0)
WRITE BUFFER
DATA 0
DATA 1
|
|
|
|
DATA N
Peripheral DMA
Controller
Peripheral ^{NODE ACTION = PUBLISH}
bus
RXRDY
USART LIN
CONTROLLER
READ BUFFER
DATA 0
|
|
|
|
DATA N
Peripheral DMA
Controller
NODE ACTION = SUBSCRIBE
Peripheral
bus
RXRDY
USART LIN
CONTROLLER
TXRDY
Figure 24-40. Master Node with Peripheral DMA Controller (LINMR.PDCM=1)
WRITE BUFFER
WRITE BUFFER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
DLC
IDENTIFIER
DATA 0
|
|
|
|
DATA N
Peripheral NODE ACTION = PUBLISH
bus
IDENTIFIER
Peripheral DMA
Controller
RXRDY
USART LIN
CONTROLLER
READ BUFFER
DATA 0
|
|
|
|
DATA N
Peripheral DMA
Controller
Peripheral ^{NODE ACTION = SUBSCRIBE}
bus
RXRDY
USART LIN
CONTROLLER
TXRDY
24.6.12.2
Slave Node Configuration
In this mode, the Peripheral DMA Controller transfers only data. The user reads the Identifier
from LINIR, and selects LIN mode by writing to LINMR. When NACT=PUBLISH the data is in the
write buffer, while the read buffer contains the data when NACT=SUBSCRIBE.
IMPORTANT: If in slave mode, LINMR.NACT is already configured correctly as PUBLISH, the
LINMR register must still be written with this value in order to set CSR.TXRDY, and to request
the corresponding Peripheral DMA Controller write transfer.
42023C–SAM–02/2013
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