SAM4L Datasheet, PDF (498/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

Figure 21-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge
ATSAM4L4/L2
CLK_SYNC
EXTINTn/NMI
ISR.INTn:
FILTER off
ISR.INTn:
FILTER on
Figure 21-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge
CLK_SYNC
EXTINTn/NMI
ISR.INTn:
FILTER off
ISR.INTn:
FILTER on
21.6.3
Non-Maskable Interrupt
The NMI supports the same features as the external interrupts, and is accessed through the
same registers. The description in Section 21.6.1 should be followed, accessing the NMI bit
instead of the INTn bits.
The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution
mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled
by accessing the registers in the EIC.
21.6.4
Asynchronous Interrupts
Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC reg-
ister. This will route the interrupt signal through the asynchronous path of the module. All edge
interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is config-
ured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted
as low level, and a one in EDGE.INTn will be interpreted as high level.
EIC_WAKE will be set immediately after the source triggers the interrupt, while the correspond-
ing bit in ISR and the interrupt to the NVIC will be set on the next rising edge of CLK_SYNC.
Refer to Figure 21-4 on page 499 for details.
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