SAM4L Datasheet, PDF (360/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
RXINI should always be cleared before clearing FIFOCON to avoid missing an RXINI event.
Figure 17-17. Example of an IN pipe with one data bank
IN
RXINI
DATA
(bank 0)
ACK
HW
SW
IN
DATA
(bank 0)
ACK
HW
SW
FIFOCON
read data from CPU _SW
BANK 0
Figure 17-18. Example of an IN pipe with two data banks
IN
DATA
(bank 0)
ACK
IN
DATA
(bank 1)
RXINI
HW
SW
read data from CPU
BANK 0
ACK
HW
SW
FIFOCON
read data from CPU _SW
BANK 0
read data from CPU
BANK 1
• Multi packet mode for IN pipes
See ”Multi packet mode for OUT endpoints” on page 351 and just replace OUT endpoints with
IN pipe.
17.6.3.12 Management of OUT pipes
• Overview
OUT packets are sent by the host. All the data can be written, acknowledging whether or not the
bank is full.
• Detailed description
The pipe and its descriptor in RAM must be pre configured.
When the current bank is clear, the Transmitted OUT Data Interrupt (TXOUTI) and FIFO Control
(UPSTAn.FIFOCON) bits will be set simultaneously. This triggers a PnINT interrupt if the Trans-
mitted OUT Data Interrupt Enable bit (UPCONn.TXOUTE) is one.
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