SAM4L Datasheet, PDF (782/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
29.8.1 Control Register
Name:
CR
Access Type:
Write-only
Offset:
0x00
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
SWRST
-
5
TXDIS
4
TXEN
3
CKDIS
2
CKEN
1
RXDIS
0
RXEN
The Control Register should only be written to enable the IISC after the chosen configuration has been written to the Mode
Register, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs. The proper sequence is to write the MR
register, then write the CR register to enable the IISC, or to disable the IISC before writing a new value into MR.
• SWRST: Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all the registers in the module. The module will be disabled after the reset.
This bit always reads as zero.
• TXDIS: Transmitter Disable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the IISC Transmitter. SR.TXEN will be cleared when the Transmitter is effectively stopped.
• TXEN: Transmitter Enable
Writing a zero to this bit has no effect.
Writing a one to this bit enables the IISC Transmitter, if TXDIS is not one. SR.TXEN will be set when the Transmitter is effectively
started.
• CKDIS: Clocks Disable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the IISC clocks generation.
• CKEN: Clocks Enable
Writing a zero to this bit has no effect.
Writing a one to this bit enables the IISC clocks generation, if CKDIS is not one.
• RXDIS: Receiver Disable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the IISC Receiver. SR.TXEN will be cleared when the Transmitter is effectively stopped.
• RXEN: Receiver Enable
Writing a zero to this bit has no effect.
Writing a one to this bit enables the IISC Receiver, if RXDIS is not one. SR.RXEN will be set when the Receiver is effectively
started.
42023C–SAM–02/2013
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