SAM4L Datasheet, PDF (622/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
24.7.3 Interrupt Enable Register
Name:
IER
Access Type:
Write-only
Offset:
0x08
Reset Value:
0x00000000
31
LINHTE
30
LINSTE
29
LINSNRE
28
LINCE
27
LINIPE
26
LINISFE
25
LINBE
24
MANEA
23
22
21
20
19
18
17
16
–
–
–
MANE
CTSIC
DCDIC
DSRIC
RIIC
15
LINTC
14
LINID
13
NACK/LINBK
12
RXBUFF
11
10
9
8
–
ITER/UNRE TXEMPTY
TIMEOUT
7
6
5
4
PARE
FRAME
OVRE
–
3
2
1
0
–
RXBRK
TXRDY
RXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
• LINHTE: LIN Header Time-out Error
• LINSTE: LIN Sync Tolerance Error
• LINSNRE: LIN Slave Not Responding Error
• LINCE: LIN Checksum Error
• LINIPE: LIN Identifier Parity Error
• LINISFE: LIN Inconsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Input Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has
the same effect. The corresponding bit in CSR and the corresponding interrupt request are named MANERR.
42023C–SAM–02/2013
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