SAM4L Datasheet, PDF (1042/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
39.6.11
Contrast Adjustment
Contrast is defined by the maximum value of V_LCD. The higher value the higher contrast.
Fine Contrast value (FCST) in CFG register is a signed value (two’s complement) which defines
the maximum voltage V_LCD on segment and common terminals. New value takes effect at the
beginning of next frame.
V_LCD = 3V + (FCST × 0, 016V )
39.6.12 Interrupts
LCDCA can generate an interrupt at the beginning of a frame. When Frame Counter 0 Rollover
bit (SR.FC0R) is set to one and interrupt is not masked, LCDCA interrupt is pending.
Moreover Frame Counter 0 (TIM.FC0) can be used to select the interrupt period generation.
This mode can provide a useful time base to update LCD.
If TIM.FC0PB=0:
Interrupt Period = ((TIM.FC0 × 8) + 1) × Frame Period
If TIM.FC0PB=1:
Interrupt Period = (TIM.FC0 + 1) × Frame Period
Note that in low power waveform mode, frame period is twice the frame period in standard wave-
form mode.
An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER) and cleared by writing a one to the corresponding bit in the Interrupt Disable Reg-
ister (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by
writing a one to the corresponding bit in Status Clear Register (SCR).
39.6.13
LCD Wake Up
LCD controller can wake up CPU with the interrupt request line. But in Power Save Mode where
APB clocks are off, LCD wake up mechanism must be enabled to wake up CPU.
Wake up mechanism is enabled by writing a one to the Wake up Enable (WEN) bit in configura-
tion register. It is disabled by writing a one to the Wake up Disable bit (WDIS). Moreover LCDCA
interrupt request must not be masked (see previous section) and LCDCA bit in Asynchronous
Wake Up Enable register (AWEN.LCDCA) must be set to one (see Power Manager chapter).
Wake up signal is generated when frame counter 0 rolls over. When wake up is detected in
Power Manager, system clocks are running therefore SR.FC0R is set to one and LCDCA irq is
generated. CPU is then woken up.
Wake up signal is cleared by disabling wake up mechanism.
39.6.14
LCD Power Supply
To operate correctly, LCD controller requires a reference level. The External BIAS bit (XBIAS) in
CFG register selects the source of V _LCD. If XBIAS is zero, V _LCD sources voltages from the inter-
nal bandgap reference. Otherwise, V _LCD must be powered externally.
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