SAM4L Datasheet, PDF (480/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 20-5. Window Mode WDT Timing Diagram, clearing within T_tban, resulting in watchdog reset.
t=t₀
T_tban
T_psel
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
20.5.3
Interrupt Mode
In interrupt mode, the WDT can generate an interrupt request when the WDT counter times out.
Interrupt mode is enabled by writing a one to the Interrupt Mode bit in the CTRL register
(CTRL.IM). When interrupt mode is enabled, the Watchdog Interrupt bit in the Interrupt Status
Register (ISR.WINT) is set when the WDT counter times out. An interrupt request will be gener-
ated if the Watchdog Interrupt bit in the Interrupt Mask Register (IMR.WINT) is set, see Figure
20-6. IMR.WINT is set by writing a one to the Watchdog Interrupt bit in the Interrupt Enable Reg-
ister (IER.WINT), and cleared by writing a one to the Watchdog Interrupt bit in the Interrupt
Disable Register (IDR.WINT). The interrupt request remains active until ISR.WINT is cleared by
writing a one to WINT in the Interrupt Clear Register (ICR.WINT).
If the Watchdog interrupt is not cleared before the next WDT counter timeout, a WDT reset is
generated, see Figure 20-7.
Note that ISR.WINT will not be cleared by the WDT reset. If ISR.WINT is not cleared manually
after a WDT reset, a new WDT reset will be issued on the first WDT counter timeout after the
reset.
Interrupt mode can be enabled in both normal and window mode.
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