SAM4L Datasheet, PDF (478/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

Figure 20-2. Basic Mode WDT Timing Diagram, Normal Operation
t=t₀
T_psel
ATSAM4L4/L2
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
Figure 20-3. Basic Mode WDT Timing Diagram, No Clear within T_psel
t=t₀
T_psel
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
20.5.1.6
Watchdog Reset
A watchdog reset will result in a reset and the code will start executing from the boot vector, refer
to Section 10. ”Power Manager (PM)” on page 102 for details. If the Disable After Reset (DAR)
bit in the CTRL Register is zero, the WDT counter will restart counting from zero when the
watchdog reset is released.
If the CTRL.DAR bit is one the WDT will be disabled after a watchdog reset. Only the CTRL.EN
bit will be changed after the watchdog reset. However, if WDTAUTO fuse is configured to enable
the WDT after a watchdog reset, and the CTRL.FCD bit is zero, writing a one to the CTRL.DAR
bit will have no effect.
20.5.2
Window Mode
The window mode can protect against tight loops of runaway code. This is obtained by adding a
ban period to timeout period. During the ban period clearing the WDT counter is not allowed.
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