SAM4L Datasheet, PDF (348/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
17.6.2.15 Management of IN endpoints
• Overview
IN packets are sent by the USBC device controller upon IN requests from the host.
The endpoint and its descriptor in RAM must be pre configured (see section ”RAM manage-
ment” on page 343 for more details).
When the current bank is clear, the TXINI and FIFO Control (UECONn.FIFOCON) bits will be set
simultaneously. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable
(TXINE) bit in UECONn is one.
TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable
Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the
interrupt. This has no effect on the endpoint FIFO.
The user writes the IN data to the bank referenced by the EPn descriptor and allows the USBC
to send the data by writing a one to the FIFO Control Clear (UECONnCLR.FIFOCONC) bit. This
will also cause a switch to the next bank if the IN endpoint is composed of multiple banks. The
TXINI and FIFOCON bits will be updated accordingly.
TXINI should always be cleared before clearing FIFOCON to avoid missing an TXINI event.
Figure 17-9. Example of an IN endpoint with one data bank
NAK
IN
DATA
(bank 0)
ACK
IN
TXINI
SW
HW
SW
FIFOCON
write data to CPU
SW
BANK 0
write data to CPU
SW
BANK 0
Figure 17-10. Example of an IN endpoint with two data banks
TXINI
SW
IN
DATA
(bank 0)
SW
ACK
IN
HW
SW
DATA
(bank 1)
ACK
FIFOCON
write data to CPU SW
BANK 0
write data to CPU SW
BANK 1
write data to CPU
BANK0
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