SAM4L Datasheet, PDF (1067/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
40.5.1 I/O Lines
The PARC pins are multiplexed with other peripherals. The user must first configure the I/O Con-
troller to give control of the pins to the PARC.
40.5.2
Power Management
PARC stops functioning when the system enters a sleep mode that disables its clock.
40.5.3 Clocks
The clock for PARC (CLK_PARC) is generated by the Power Manager. It can be disabled either
manually through the user interface of the Power Manager or automatically when the system
enters a sleep mode that disables the clocks to the peripheral bus modules. For correct behav-
ior, CLK_PARC frequency must be at least twice the PCCK frequency.
40.5.4 DMA
The PARC DMA handshake interface is connected to the Peripheral DMA Controller (PDCA).
Using the PARC DMA functionality requires the PDCA to be configured first.
40.5.5 Interrupt
The PARC interrupt request line is connected to the NVIC. Using the PARC interrupt requires
the NVIC to be configured first.
40.5.6
Peripheral Events
The PARC peripheral events are connected via the Peripheral Event System. Refer to Section
31. ”Peripheral Event Controller (PEVC)” on page 839 for details.
40.6 Functional Description
40.6.1
Capture Operation
PARC is enabled by writing a one to the Enable bit in the Control Register (CR.EN). Data cap-
ture is enabled by writing a one to the Start bit in the Control Register (CR.START) and stopped
by writing a one to the Stop bit in the Control Register (CR.STOP).
Data capture is made by sampling the data bus PCD[7:0] on the rising or falling edge of the
PCCK input clock then re-synchronized to the PB clock domain. PCCK sampling edge is
selected with EDGE bit in the Configuration Register (CFG.EDGE). User can select a sampling
condition to capture the data. There are four modes defined by Sampling Mode field
(CFG.SMODE): when PCEN1 is high, when PCEN1 and PCEN2 are high, when PCEN1 or
PCEN2 is high and in last mode data is sampled without condition.
Data can be captured every two cycles if CFG.HALF bit is set to one. It can be used, for exam-
ple, to capture the luminance Y of a CMOS digital image sensor. In addition, bit CFG.ODD
specifies which of odd or even bytes are captured. Considering that first byte captured (byte 0),
after reset, is an even byte.
Captured data are stored in the Receive Holding Register (RHR). Concatenated data can also
be stored in RHR to make a 16-bit or a 32-bit data, with the first byte received in LSB position.
Concatenated data size is configured by Data Size bit in CFG register (CFG.DSIZE). When the
configured data bytes are captured, the Data Ready bit is set to one in the Status Register
(SR.DRDY). DRDY is also set to one when internal buffer is not full but CR.STOP is set to one or
stop event occurs (see “Peripheral Events” ).
42023C–SAM–02/2013
1067