SAM4L Datasheet, PDF (359/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
– DTGLER: Is set if a Data toggle error occurs during a USB transaction.
17.6.3.9
Multi packet mode and single packet mode.
See ”Multi packet mode and single packet mode.” on page 346 and just consider that an OUT
pipe corresponds to an IN endpoint, and an IN pipe corresponds to an OUT endpoint.
17.6.3.10
Management of control pipes
A control transaction is composed of three stages:
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
The user has to change the pipe token according to each stage.
For control pipes only, the token is assigned a specific initial data toggle sequence:
• SETUP: Data0
• IN: Data1
• OUT: Data1
17.6.3.11 Management of IN pipes
• Overview
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be read, acknowledging whether or not the bank is empty.
• Detailed description
The pipe and its descriptor in RAM must be pre configured.
The host can request data from the device in two modes, selected by writing to the IN Request
Mode bit in the Pipe n IN Request register (UPINRQn.INMODE):
• When INMODE is written to zero, the USBC will perform INRQ IN requests before freezing
the pipe.
• When INMODE is written to one, the USBC will perform IN requests as long as the pipe is not
frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (UPCONn.PFREEZE is zero).
When the current bank is full, the RXINI and FIFO Control (UPSTAn.FIFOCON) bits will be set
simultaneously. This triggers a PnINT interrupt if the Received IN Data Interrupt Enable bit
(UPCONn.RXINE) is one.
RXINI shall be cleared by software to acknowledge the interrupt. This is done by writing a one to
the Received IN Data Interrupt Clear bit in the Pipe n Control Clear register
(UPCONnCLR.RXINIC), which does not affect the pipe FIFO.
The user reads the byte count of the current bank from the descriptor in RAM
(Pn_PCKSIZE_BK0/1.BYTE_COUNT) to know how many bytes should be read.
The user reads the IN data from the RAM and clears the FIFOCON bit to free the bank. This will
also cause a switch to the next bank if the IN endpoint is composed of multiple banks. The RXINI
and FIFOCON bits will be updated accordingly.
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