SAM4L Datasheet, PDF (475/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
20. Watchdog Timer (WDT)
Rev.: 5.0.1.0
20.1 Features
• Watchdog Timer counter with 32-bit counter
• Timing window watchdog
• Clocked from system RC oscillator or one of the 32 KHz oscillator (OSC32 or RC32)
• Configuration lock
• WDT may be enabled at reset by a fuse
20.2 Overview
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The WDT has an internal counter clocked from the system RC oscillator or one of the 32kHz
oscillator.
The WDT counter must be periodically cleared by software to avoid a watchdog reset. If the
WDT timer is not cleared correctly, the device will reset and start executing from the boot vector.
If the WDT is configured in interrupt mode an interrupt request will be generated on the first tim-
eout and a reset on the second timeout if the interrupt has not been cleared.
20.3 Block Diagram
Figure 20-1. WDT Block Diagram
PB
PB Clock Domain
RCSYS ₀
OSC32K ¹
CEN
CSSEL
CLR
WDTCLR
SR
WINDOW,
CLEARED
SYNC
CTRL
EN, MODE,
PSEL, TBAN
CLK_CNT _{32-bit Counter}
CLK_CNT Domain
Watchdog
Detector
Watchdog
Reset
Watchdog
Interrupt
20.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
42023C–SAM–02/2013
475