SAM4L Datasheet, PDF (776/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
29.6.5
Serial Clock and Word Select Generation
The generation of clocks in the IISC is described in Figure 29-3 on page 777.
In Slave mode, the Serial Clock and Word Select Clock are driven by an external master. ISCK
and IWS pins are inputs and no generic clock is required by the IISC.
In Master mode, the user can configure the Master Clock, Serial Clock, and Word Select Clock
through the Mode Register (MR). IMCK, ISCK, and IWS pins are outputs and a generic clock is
used to derive the IISC clocks.
Audio codecs connected to the IISC pins may require a Master Clock signal with a frequency
multiple of the audio sample frequency (fs), such as 256fs. When the IISC is in Master mode,
writing a one to MR.IMCKMODE will output GCLK_IISC as Master Clock to the IMCK pin, and
will divide GCLK_IISC to create the internal bit clock, output on the ISCK pin. The clock division
factor is defined by writing to MR.IMCKFS and MR.DATALENGTH, as described ”IMCKFS:
Master Clock to fs Ratio” on page 783.
The Master Clock (IMCK) frequency is 16*(IMCKFS+1) times the sample frequency (fs), i.e. IWS
frequency. The Serial Clock (ISCK) frequency is 2*Slot Length times the sample frequency (fs),
where Slot Length is defined in Table 29-2 on page 776.
Table 29-2. Slot Length
MR.DATALENGTH
Word Length
0
32 bits
1
24 bits
2
20 bits
3
18 bits
4
16 bits
5
16 bits compact stereo
6
8 bits
7
8 bits compact stereo
Slot Length
32
32 if MR.IWS24 is zero
24 if MR.IWS24 is one
16
8
Warning: MR.IMCKMODE should only be written as one if the Master Clock frequency is strictly
higher than the Serial Clock.
If a Master Clock output is not required, the GCLK_IISC generic clock is used as ISCK, by writ-
ing a zero to MR.IMCKMODE. Alternatively, if the frequency of the generic clock used is a
multiple of the required ISCK frequency, the IMCK to ISCK divider can be used with the ratio
defined by writing the MR.IMCKFS field.
The IWS pin is used as Word Select as described in Section 29.6.4 ”I2S Reception and Trans-
mission Sequence” on page 775.
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