SAM4L Datasheet, PDF (164/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
– Set on 0 to 1 transition on the PCLKSR.BOD33SYNRDY bit is detected.
• BOD18DET - Brown out 1.8 Detected:
– Set on 0 to 1 transition on the PCLKSR.BOD18DET bit is detected.
• BOD33DET - Brown out 3.3 Detected:
– Set on 0 to 1 transition on the PCLKSR.BOD33DET bit is detected.
• RC32KSAT- RC32K FINE value saturated:
– 0: The RC32K autocalibration has not saturated the FINE value.
– 1: The RC32K autocalibration has brought FINE into saturation.
• RC32KREFE - RC32K Reference error:
– 0: The RC32K has detected a running reference frequency.
– 1: The RC32K reference frequency has stopped.
• RC32KLOCK - RC32K Locked to reference:
– 0: The RC32K has not obtained a lock to the reference frequency.
– 1: The RC32K has obtained alock to the reference frequency.
• RC32KRDY - RC32K Ready:
– 0: Reads from FINE and COARSE will yield invalid values. Writes to FINE and
COARSE is not yet complete
– 1: FINE and COARSE can be read, writes to FINE and COARSE have been
commited.
• OSC32RDY - 32kHz Oscillator Ready:
– A 0 to 1 transition on the PCLKSR.OSC32RDY bit is detected.
The interrupt sources will generate an interrupt request if the corresponding bit in the Interrupt
Mask Register is set. The interrupt sources are ORed together to form one interrupt request. The
BSCIF will generate an interrupt request if at least one of the bits in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt
Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear
Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from
the BSCIF will remain active until all the bits in ISR are cleared.
42023C–SAM–02/2013
164