SAM4L Datasheet, PDF (413/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
• DTSEQ: Data Toggle Sequence
This field indicates the data PID of the current bank.
For OUT pipes, this field indicates the data toggle of the next packet that will be sent.
For IN pipes, this field indicates the data toggle of the received packet stored in the current bank.
DTSEQ
0
0
0
1
1
0
1
1
Data toggle sequence
Data0
Data1
reserved
reserved
• RXSTALLDI: Received STALLed Interrupt
This bit is cleared when the RXSTALLDIC bit is written to one.
This bit is set, for all endpoints (except isochronous), when a STALL handshake has been received on the current bank of the
pipe. The pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.
• CRCERRI: CRC Error Interrupt
This bit is cleared when the CRCERRIC bit is written to one.
This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the pipe. This triggers an interrupt if
the TXSTPE bit is one.
• ERRORFI: Errorflow Interrupt
This bit is cleared when the ERRORFIC bit is written to one.
This bit is set:
- for isochronous and interrupt IN/OUT pipes, when an error flow occurs. This triggers an interrupt if the ERRORFIE bit is one.
- for isochronous or interrupt OUT pipes, when a transaction underflow occurs in the current pipe. i.e, the pipe can’t send the
OUT data packet in time because the current bank is not ready.
- for isochronous or interrupt IN pipes, when a transaction flow error occurs in the current pipe. i.e, the current bank of the pipe
is not free when a new IN USB packet is received. This packet is not stored in the bank. For interrupt pipes, the overflowed
packet is ACKed to respect the USB standard.
• NAKEDI: NAKed Interrupt
This bit is cleared when the NAKEDIC bit is written to one.
This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.
• PERRI: Pipe Error Interrupt
This bit is cleared when the PERRIC bit is written to one.
This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to
the PERSTA structure of the pipe descriptor (Figure 17-8) to determine the source of the error.
• TXSTPI: Transmitted SETUP Interrupt
This bit is cleared when the TXSTPIC bit is written to one.
This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the
TXSTPE bit is one.
• TXOUTI: Transmitted OUT Data Interrupt
This bit is cleared when the TXOUTIC bit is written to one.
This bit is set when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is one.
• RXINI: Received IN Data Interrupt
This bit is cleared when the RXINIC bit is written to one.
This bit is set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the RXINE bit is
one.
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