SAM4L Datasheet, PDF (424/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

42023C–SAM–02/2013
ATSAM4L4/L2
The input data for processing is written to an input buffer consisting of four 32-bit registers
through the Input Data (IDATA) register address. The input buffer register that is written to when
the next write is performed is indicated by the Input Data Word (IDATAW) field in the Data Buffer
Pointer (DATABUFPTR) register. This field is incremented by one or wrapped by hardware
when a write to the IDATA register address is performed. This field can also be programmed,
allowing the user direct control over which input buffer register to write to. Note that when AESA
is in the CFB operation mode with the data segment size less than 128 bits, the input data must
be written to the first (i.e., DATABUFPTR.IDATAW = 0) and/or second (i.e.,
DATABUFPTR.IDATAW = 1) input buffer registers (see Table 18-1 on page 424).
Once the input data is written to the input buffer, data processing starts automatically. After the
content of the input buffer has been transferred out, the Input Buffer Ready (IBUFRDY) bit in the
Status Register (SR) is set by hardware (which triggers an interrupt request if the corresponding
IBUFRDY bit in the Interrupt Enable Register (IER) is programmed to ‘1’). This bit is cleared by
hardware when new input data is written to the relevant input buffer registers.
An initialization vector or an initial counter is required as an input to the encryption and decryp-
tion processes for all confidentiality modes of operation, except the ECB operation mode (see
Section 18.4.2 on page 425). The initialization vector or initial counter is written to the four 32-bit
Initialization Vector (INITVECT) registers. Note that access to the INITVECT registers is by 32-
bit words only (i.e., no halfword or byte access).
When data processing has completed, the Output Data Ready (ODATARDY) bit in the SR is set
by hardware (which triggers an interrupt request if the corresponding ODATARDY bit in the IER
is programmed to ‘1’). The processed output data is read out through the Output Data (ODATA)
register address from the output buffer consisting of four 32-bit registers. The output buffer reg-
ister that is read from when the next read is performed is indicated by the Output Data Word
(ODATAW) field in the DATABUFPTR register. This field is incremented by one or wrapped by
hardware when a read from the ODATA register address is performed. This field can also be
programmed, giving the user direct control over which output buffer register to read from. Note
that when AESA is in the CFB operation mode with the data segment size less than 128 bits, the
output data must be read from the first (i.e., DATABUFPTR.ODATAW = 0) and/or second (i.e.,
DATABUFPTR.ODATAW = 1) output buffer registers (see Table 18-1 on page 424). The SR.ODA-
TARDY bit is cleared by hardware after the processed data has been read from the relevant
output buffer registers.
Table 18-1. Relevant Input/Output Buffer Registers for Respective Confidentiality Modes of
Operation
Confidentiality Mode of Operation Relevant Input/Output Buffer Registers
ECB
All
CBC
All
OFB
All
128-bit CFB
All
64-bit CFB
First and second
32-bit CFB
First
16-bit CFB
First
8-bit CFB
First
CTR
All
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