SAM4L Datasheet, PDF (422/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
18. Advanced Encryption Standard (AESA)
Rev: 1.0.2.0
18.1 Features
• Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
• 128-bit cryptographic key
• Five confidentiality modes of operation as recommended in NIST Special Publication 800-38A,
Recommendation for Block Cipher Modes of Operation - Methods and Techniques:
– Electronic Code Book
– Cipher Block Chaining
– Cipher Feedback
– Output Feedback
– Counter
• Short encryption and decryption time of 11 clock cycles with 128-bit cryptographic key
• Buffering of input and output data for non-stop processing of multiple data blocks
• DMA interface for multiple data block processing with minimal CPU intervention
• Hardware countermeasures against differential power analysis attacks
•
18.2 Overview
The Advanced Encryption Standard module (AESA) is compliant with the FIPS (Federal Infor-
mation Processing Standard) Publication 197, Advanced Encryption Standard (AES), which
specifies a symmetric block cipher that is used to encrypt and decrypt electronic data. Encryp-
tion is the transformation of a usable message, called the plaintext, into an unreadable form,
called the ciphertext. On the other hand, decryption is the transformation that recovers the plain-
text from the ciphertext.
AESA supports 128 bits cryptographic key size.
AESA supports all five confidentiality modes of operation (Electronic Code Book (ECB), Cipher
Book Chaining (CBC), Cipher Feedback (CFB), Output Feedback (OFB), and Counter (CTR)) for
symmetric key block cipher algorithms as recommended in the NIST (National Institute of Stan-
dards and Technology) Special Publication 800-38A, Recommendation for Block Cipher Modes
of Operation - Methods and Techniques (see Section 18.4.2 on page 425). For the CFB mode,
AESA supports data segment sizes of 8, 16, 32, 64, and 128 bits.
AESA requires 11 clock cycles to process one block (128 bits) of input data, where N_r is the
number of rounds required to process one data block and is 10 when the key size is 128 bits.
The relationship between the module’s clock frequency and throughput (in bytes per second) is
given by
Clock Frequency = _⎝⎛^T----^h----^r--^o---1^u---6^g----^h---^p---^u----^t_⎠⎞ × (11)
AESA is able to process multiple data blocks without stopping. This is due to the buffering of the
input and output data within the module, which allows a new data block to be written to and the
previous data block to be read from it while the current data block is being processed.
AESA is able to interface with a DMA controller, thus allowing the processing of multiple data
blocks with minimal CPU intervention. Two channels are supported by the DMA interface - one
for writing data to AESA and one for reading data from AESA.
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