SAM4L Datasheet, PDF (135/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
11.4.2 Interrupts
The BPM interrupt line is connected to the NVIC. Using the BPM interrupt requires the NVIC to
be programmed first.
11.4.3
Debug Operation
If a BACKUP mode is requested by the system while in debug mode, the core domain is kept to
those in RUN mode, and the debug modules are kept running to allow the debugger to access
internal registers.
When exiting the BACKUP mode upon a wakeup event, all the core domain is reset but the
debug session. It allows the user to keep using its current debug session.
Note: Hot plugging in backup mode is not supported.
11.5 Functional Description
11.5.1
Power Scaling
The power scaling feature is programmed thanks to the PMCON register where the user can
select the Power Scaling Configuration (PS) and the Power Scaling Change Request
(PSCREQ).
When exiting the BACKUP mode, the Power Scaling Configuration field (PMCON.PS) is
unchanged. It ensures that the system is running in the same power scaling configuration.
When a reset occurs (See ”Reset Description” on page 106.), the PMCON.PS field is reset to its
default value, and then, the system goes back to the reset power configuration mode (RUN0
mode).
Refer to the Low Power Technique chapter (See ”Power Scaling” on page 52.) to understand the
sequence to apply.
11.5.2
Power Save Modes
The Power Save Mode feature is supported thanks to the PMCON register where the user can
select the SLEEP mode configuration (SLEEP), the BACKUP mode (BKUP) and the RETEN-
TION mode (RET). The SLEEPDEEP bit located in the System Control Register in the Cortex
M4 should also be used to manage the different Power Save Modes.
The selected power save mode is entered after a WFI instruction.
Refer to the Low Power Technique chapter (See ”Power Scaling” on page 52.) to have more
details.
11.5.3
I/O Lines Pin Muxing in Backup Mode
In all modes including the BACKUP mode, a subset of pins (external interrupts) can be directly
routed to a list of peripheral function bypassing the GPIO controller.
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