SAM4L Datasheet, PDF (204/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
13.6.3.6
13.6.3.7
If a one is written to DFLLxCONF.STABLE, DFLLxVAL.FINE will never change after Fine Lock is
set. The frequency will be measured and the error value can be read from the
DFLLxRATIO.RATIODIFF.
It is possible to change the value of DFLLxCONF.STABLE while in lock, without loosing the
locks. This enables the user to let the DFLLx compensate for drift if DFLLxRATIO.RATIODIFF is
too big, and having a stable frequency when this is required.
Reference clock stop detection
If CLK_DFLLx_REF stops or is running at a very slow frequency, the DFLLx Reference Clock
Stopped bit in PCLKSR will be set (PCLKSR.DFLLxRCS). Note that the detection of a stopped
reference clock will take a long time. The DFLLx operate as if it was in open loop mode if it
detects that the reference clock has stopped. Closed loop mode operation will automatically
resume if the CLK_DFLLx_REF is restarted. An interrupt can be generated on a zero-to-one
transition on PCLKSR.DFLLxRCS.
Dealing With Delay in the DFLL
The time from selecting a new CLK_DFLLx frequency until this frequency is output by the
DFLLx, can be up to several micro seconds. If the difference between the desired output fre-
quency (CLK_DFLLx) and the frequency of CLK_DFLLx_REF is small this can lead to an
instability in the DFLLx locking mechanism, which can prevent the DFLLx from achieving locks.
To avoid this, a chill cycle where the CLK_DFLLx frequency is not measured can be enabled.
The chill cycle is enabled by default, but can be disabled by writing a one to the Chill Cycle Dis-
able bit in DFLLxCONF (DFLLxCONF.CCDIS). Enabling chill cycles might double the lock time.
Another solution to the same problem is to use less strict lock requirements. This is called Quick
Lock (QL), which is also enabled by default, but can be disabled by writing a one to the Quick
Lock Disable bit in DFLLxCONF (DFLLxCONF.QLDIS). The QL might lead to bigger spread in
the outputted frequency than chill cycles, but the average output frequency is the same.
If the target frequency is below 40MHz, one of these should always be enabled.
Spread Spectrum Generator (SSG)
When CLK_DFLLx is used as the main clock source for the device, the EMI radiated from the
device will be synchronous to f_{CLK_DFLLx}. To provide better Electromagnetic Compatibility (EMC)
DFLLx can provide a clock with the energy spread in the frequency domain (spread spectrum).
This is done by adding or subtracting values from the FINE value. SSG is enabled by writing a
one to the Enable bit in the DFLLx Spread Spectrum Generator Control Register (DFLLx-
SSG.EN). The Spread Spectrum Generator Block Diagram is shown in Figure 13-5.
Figure 13-5. Spread Spectrum Generator Block Diagram.
CLK_DFLLx_SSG
Pseudorandom
Binary Sequence
FINE
Spread Spectrum
Generator
To DAC
8
AMPLITUDE,
STEPSIZE
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