SAM4L Datasheet, PDF (601/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 24-37. Slave Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE)
TXRDY
RXRDY
LINIDRX
Read
LINID
Read
RHR
LINTC
Break
Synch
Protected
Identifier
Data 1
Data N-1
Data N
Checksum
Data 1
Data N-2
Data N-1
Data N
Figure 24-38. Slave Node Configuration, LINMR.NACT is 0x2 (IGNORE)
TXRDY
RXRDY
LINIDRX
Read
LINID
Read
RHR
LINTC
Break
Synch
Protected
Identifier
Data 1
Data N-1
Data N
Checksum
24.6.12
LIN Frame Handling With The Peripheral DMA Controller
The USART can be used together with the Peripheral DMA Controller in order to transfer data
without processor intervention. The Peripheral DMA Controller uses the CSR.TXRDY and
CSR.RXRDY bits to trigger one byte writes or reads. It always writes to THR, and it always reads
RHR.
24.6.12.1
Master Node Configuration
The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration:
• LINMR.PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write
buffer.
• LINMR.PDCM=1: LIN configuration is written by the Peripheral DMA Controller to THR, and
is stored in the write buffer. Since data transfer size is a byte, the transfer is split into two
accesses. The first writes the NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS bits in the
LINMR register, while the second writes the LINMR.DLC field. If LINMR.NACT=PUBLISH,
the write buffer will also contain the Identifier.
When LINMR.NACT=SUBSCRIBE, the read buffer contains the data.
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