SAM4L Datasheet, PDF (593/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
is not received within the time defined in THeader_Maximum, the Lin Header Time-out error
(CSR.LINHTE) is generated (see Section 24.6.10.13). An interrupt request is generated if
IMR.LINHTE is set. Writing a one to CR.RSTSTA will clear CSR.LINHTE, CSR.LINBK, and
CSR.LINID.
Figure 24-28. Header Reception
Baud Rate
Clock
RXD
LINID
Break Field
13 dominant bits (at 0)
Break
Delimiter
1 recessive bit
(at 1)
Start
Bit
1
010101
Synch Byte = 0x55
0
Stop
Bit
Start
Bit
ID0
ID1
ID2
ID3
ID4 ID5
ID6
ID7
Stop
Bit
US_LINIR
Write US_CR
With RSTSTA=1
See also ”Slave Node Configuration” on page 600.
24.6.10.7
Slave Node Synchronization
Synchronization is only done by the slave, and can be disabled by writing a one to the Synchro-
nization Disable bit in the LIN Mode Register (LINMR.SYNCDIS). If the Sync byte is not 0x55, an
Inconsistent Sync Field error is generated, and the LIN Inconsistend Sync Field Error bit in CSR
(CSR.LINISFE) is set. An interrupt request is generated if the LINISFE bit in IMR is set.
CSR.LINISFE is cleared by writing a one to CR.RSTSTA. The time between falling edges is
measured by a 19-bit counter, driven by the sampling clock (see Section 24.6.4).
Figure 24-29. Sync Field
2 Tbit
Start
bit
Synch Field
8 Tbit
2 Tbit
2 Tbit
2 Tbit
Stop
bit
The counter starts when the Sync field start bit is detected, and continues for eight bit periods. If
the deviation is within ±15% (see below), the 16 most significant bits (counter value divided by 8)
becomes the new clock divider (LINBRR.LINCD), and the three least significant bits (the remain-
der) becomes the new fractional part (LINBRR.LINFP).
42023C–SAM–02/2013
593