SAM4L Datasheet, PDF (706/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

Figure 27-5. Bus Timing Diagram
t _LOW
t _HIGH
t _LOW
S
t _HD:STA
t
SU:DAT
t _HD:DAT
t _SU:DAT
ATSAM4L4/L2
t
SU:STO
P
t _SU:STA
Sr
27.8.2.3
Setting up and Performing a Transfer
Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Reg-
ister (CMDR). TWIM status is provided in the Status Register (SR). The following list presents
the main steps in a typical communication:
1. Before any transfers can be performed, bus timings must be configured by writing to the
Clock Waveform Generator Register (CWGR) and, if HS-mode is supported, the HS-
mode Clock Waveform Generator Register (HSCWGR). If operating in SMBus mode,
the SMBus Timing Register (SMBTR) register must also be configured.
2. If the Peripheral DMA Controller is to be used for the transfers, it must be set up.
3. CMDR or NCMDR must be written with a value describing the transfer to be performed.
The interrupt system can be set up to give interrupt requests on specific events or error condi-
tions in the SR, for example when the transfer is complete or if arbitration is lost. The Interrupt
Enable Register (IER) and Interrupt Disable Register (IDR) can be written to specify which bits in
the SR will generate interrupt requests.
The SR.BUSFREE bit is set when activity is completed on the two-wire bus. The SR.CRDY bit is
set when CMDR and/or NCMDR is ready to receive one or more commands.
The controller will refuse to start a new transfer while ANAK, DNAK,, ARBLST, or HSMCACK in
the Status Register (SR) is one. This is necessary to avoid a race when the software issues a
continuation of the current transfer at the same time as one of these errors happen. Also, if
ANAK or DNAK occurs, a STOP condition is sent automatically. The user will have to restart the
transmission by clearing the error bits in SR after resolving the cause for the NACK.
After a data or address NACK from the slave, a STOP will be transmitted automatically. Note
that the VALID bit in CMDR is NOT cleared in this case. If this transfer is to be discarded, the
VALID bit can be cleared manually allowing any command in NCMDR to be copied into CMDR.
When a data or address NACK is returned by the slave while the master is transmitting, it is pos-
sible that new data has already been written to the THR register. This data will be transferred out
as the first data byte of the next transfer. If this behavior is to be avoided, the safest approach is
to perform a software reset of the TWIM.
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