SAM4L Datasheet, PDF (912/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
34.3 Block Diagram
Figure 34-1. CATB Block Diagram
SENSE0
.
.
.
SENSEn
CLK_ACQ
Capacitance
PINSEL Counter
Filter
CKSEL
Threshold
DIS
TOP
LEVEL
SPREAD
TIDLE IDLE
THRESH
REPEAT TLEVEL RAW
LENGTH
CHARGET
Interface Registers
RC oscillator
GCLK
INTERRUPT
34.4 I/O Lines Description
CLK_CATB _{Peripheral Bus} DMA Control
Table 34-1. I/O Lines Description
Pin Name
Pin Description
SENSE[n:0]
Capacitive sense line
DIS
Capacitive discharge line
Type
Input/Output
Output
34.5 Product Dependencies
In order to use the CATB module, other parts of the system must be configured correctly, as
described below.
34.5.1 I/O Lines
The CATB pins may be multiplexed with the I/O Controller lines. The user must first configure
the I/O Controller to assign the desired CATB pins to their peripheral functions.
34.5.2
Power Management
If the CPU enters a sleep mode that disables clocks used by the CATB, it will stop functioning
and the CATB must be reinitialized to resume operation after the system wakes up from sleep
mode. Ongoing measurements will be invalid. The CATB can automatically request clocks when
using the Peripheral Event System. The CATB is able to wake the system from sleep mode
using interrupts.
34.5.3 Clocks
The clock for the CATB bus interface (CLK_CATB) is generated by the Power Manager (PM).
This clock is enabled at reset, and can be disabled in the PM. It is recommended to disable the
CATB before disabling this clock, in order to avoid freezing the CATB in an undefined state.
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