SAM4L Datasheet, PDF (256/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
14. Flash Controller (FLASHCALW)
Rev: 1.1.0.1
14.1 Features
• Controls on-chip flash memory
• Supports 0 and 1 wait state bus access
• Flash Read-Standby mode to achieve very low power flash operation
• Unified direct mapped PicoCache to minimize flash active power and improve performance
• 32-bit HSB interface for reads from flash and writes to page buffer
• 32-bit PB interface for issuing commands to and configuration of the controller
• 32-bit HSB interface for reads and writes to the PicoCache RAM when it is disabled
• Flash memory is divided into 16 regions that can be individually protected or unprotected
• Supports reads and writes of general-purpose Non Volatile Memory (NVM) bits
• Supports reads and writes of additional NVM pages
• Supports strong device protection
14.2 Overview
The Flash Controller (FLASHCALW) interfaces the on-chip flash memory with the 32-bit internal
HSB bus. The controller manages the reading, writing, erasing, locking, and unlocking
sequences. To minimize power consumption, the module is tigthly coupled to a direct mapped
cache resulting in a significant decrease of the flash active power consumption and also in a per-
formance increase when running with one wait state.
42023C–SAM–02/2013
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