SAM4L Datasheet, PDF (224/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
13.7.9 PLL Control Register
Name:
PLLn
Access Type:
Read/Write
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
-
-
PLLCOUNT
23
22
21
20
19
18
17
16
-
-
-
-
PLLMUL
15
14
13
12
11
10
9
8
-
-
-
-
PLLDIV
7
6
5
4
3
2
1
0
-
-
PLLOPT
PLLOSC
PLLEN
• PLLCOUNT: PLL Count
Specifies the number of RCSYS clock cycles before ISR.PLLLOCKn will be set after PLLn has been written, or after PLLn has
been automatically re-enabled after exiting a sleep mode.
• PLLMUL: PLL Multiply Factor
• PLLDIV: PLL Division Factor
These fields determine the ratio of the PLL output frequency to the source oscillator frequency:
f_vco = (PLLMUL+1)/PLLDIV • f_REF if PLLDIV >0
f_vco = 2•(PLLMUL+1) • f_REF if PLLDIV = 0
Note that the PLLMUL field should always be greater than 1 or the behavior of the PLL will be undefined.
• PLLOPT: PLL Option
PLLOPT[0]: Selects the VCO frequency range (f_vco).
0: 80MHz<f_vco<180MHz
1: 160MHz<f_vco<240MHz
PLLOPT[1]: Divides the output frequency by 2.
0: f_PLL= f_vco
1: f_PLL = f_vco/2
PLLOPT[2]:Wide-Bandwidth mode.
0: Wide Bandwidth Mode enabled.
1: Wide Bandwidth Mode disabled.
• PLLOSC: PLL Oscillator Select
Reference clock source select for the reference clock, refer to the “PLL Clock Sources” table in the SCIF Module
Configuration section for details.
42023C–SAM–02/2013
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