SAM4L Datasheet, PDF (497/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge,
or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL regis-
ters. Each interrupt has a bit INTn in each of these registers. Writing a zero to the INTn bit in the
MODE register enables edge triggered interrupts, while writing a one to the bit enables level trig-
gered interrupts.
If INTn is configured as an edge triggered interrupt, writing a zero to the INTn bit in the EDGE
register will cause the interrupt to be triggered on a falling edge on EXTINTn, while writing a one
to the bit will cause the interrupt to be triggered on a rising edge on EXTINTn.
If INTn is configured as a level triggered interrupt, writing a zero to the INTn bit in the LEVEL
register will cause the interrupt to be triggered on a low level on EXTINTn, while writing a one to
the bit will cause the interrupt to be triggered on a high level on EXTINTn.
Each interrupt has a corresponding bit in each of the interrupt control and status registers. Writ-
ing a one to the INTn bit in the Interrupt Enable Register (IER) enables the external interrupt
from pin EXTINTn to propagate from the EIC to the NVIC, while writing a one to INTn bit in the
Interrupt Disable Register (IDR) disables this propagation. The Interrupt Mask Register (IMR)
can be read to check which interrupts are enabled. When an interrupt triggers, the correspond-
ing bit in the Interrupt Status Register (ISR) will be set. This bit remains set until a one is written
to the corresponding bit in the Interrupt Clear Register (ICR) or the interrupt is disabled.
Writing a one to the INTn bit in the Enable Register (EN) enables the external interrupt on pin
EXTINTn, while writing a one to INTn bit in the Disable Register (DIS) disables the external inter-
rupt. The Control Register (CTRL) can be read to check which interrupts are enabled. If a bit in
the CTRL register is set, but the corresponding bit in IMR is not set, an interrupt will not propa-
gate to the NVIC. However, the corresponding bit in ISR will be set, and EIC_WAKE will be set.
Note that an external interrupt should not be enabled before it has been configured correctly.
If the CTRL.INTn bit is zero, the corresponding bit in ISR will always be zero. Disabling an exter-
nal interrupt by writing a one to the DIS.INTn bit will clear the corresponding bit in ISR.
Refer to the Module Configuration section for the number of external interrupts.
21.6.2
Synchronization and Filtering of External Interrupts
In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so
spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The syn-
chronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the
NVIC by two cycles of CLK_SYNC, see Figure 21-2 and Figure 21-3 for examples (FILTER off).
It is also possible to apply a filter on EXTINTn by writing a one to the INTn bit in the FILTER reg-
ister. This filter is a majority voter, if the condition for an interrupt is true for more than one of the
latest three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propa-
gation of the interrupt to the NVIC by one or two cycles of CLK_SYNC, see Figure 21-2 and
Figure 21-3 for examples (FILTER on).
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