SAM4L Datasheet, PDF (585/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Writing 0x2 to the MR.MODE field configures the USART to operate in hardware handshaking
mode. The receiver will drive its RTS pin high when disabled or when the Reception Buffer Full
bit (CSR.RXBUFF) is set by the Buffer Full signal from the Peripheral DMA controller. If the
receiver RTS pin is high, the transmitter CTS pin will also be high and only the active character
transmissions will be completed. Allocating a new buffer to the DMA controller by clearing
RXBUFF, will drive the RTS pin low, allowing the transmitter to resume transmission. Detected
level changes on the CTS pin are reported by the CTS Input Change bit in the Channel Status
Register (CSR.CTSIC). An interrupt request is generated if the Input Change bit in the Interrupt
Mask Register is set. CSR.CTSIC is cleared when reading CSR.
Figure 24-18 illustrates receiver functionality, and Figure 24-19 illustrates transmitter
functionality.
Figure 24-18. Receiver Behavior when Operating with Hardware Handshaking
RXD
RXEN = 1
Write
CR
RXDIS = 1
RTS
RXBUFF
Figure 24-19. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
24.6.7
Modem Mode
The USART features a modem mode, supporting asynchronous communication with the follow-
ing signal pins: Data Terminal Ready (DTR), Data Set Ready (DSR), Request to Send (RTS),
Clear to Send (CTS), Data Carrier Detect (DCD), and Ring Indicator (RI). Modem mode is
enabled by writing 0x3 to MR.MODE. The USART will behave as a Data Terminal Equipment
(DTE), controlling DTR and RTS, while detecting level changes on DSR, DCD, CTS, and RI.
Table 24-8 shows USART signal pins with the corresponding standardized modem connections.
Table 24-8. Circuit References
USART Pin
V.24
TXD
2
RTS
4
DTR
20
RXD
3
CTS
5
CCITT
103
105
108.2
104
106
Direction
From terminal to modem
From terminal to modem
From terminal to modem
From modem to terminal
From terminal to modem
42023C–SAM–02/2013
585