SAM4L Datasheet, PDF (350/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
set, or if the total byte count is not an integral multiple of EPSIZE, whereby the last packet
should be short.
To enable the multi packet mode, the user should configure the endpoint descriptor
(EPn_PCKSIZE_BK0/1.BYTE_COUNT) to the total size of the multi packet, which should be
larger than the endpoint size (EPSIZE).
Since the EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE is incremented (by the transmitted
packet size) after each successful transaction, it should be set to zero when setting up a new
multi packet transfer.
The EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE is cleared by hardware when all the bank
contents have been sent. The bank is considered as ready and the TX_IN flag is set when:
• A short packet (smaller than EPSIZE) has been transmitted.
• A packet has been successfully transmitted, the updated MULTI_PACKET_SIZE equals the
BYTE_COUNT, and the AUTO_ZLP field is not set.
• An extra zero length packet has been automatically sent for the last transfer of the current
bank, if BYTE_COUNT is a multiple of EPSIZE and AUTO_ZLP is set.
17.6.2.16 Management of OUT endpoints
• Overview
The endpoint and its descriptor in RAM must be pre configured, see section ”RAM management”
on page 343 for more details.
When the current bank is full, the RXOUTI and FIFO Control (UECONn.FIFOCON) bits will be
set simultaneously. This triggers an EPnINT interrupt if the Received OUT Data Interrupt Enable
(RXOUTE) bit in UECONn is one.
RXOUTI shall be cleared by software (by writing a one to the Received OUT Data Interrupt Clear
(RXOUTIC) bit) to acknowledge the interrupt. This has no effect on the endpoint FIFO.
The user reads the OUT data from the RAM and clears the FIFOCON bit to free the bank. This
will also cause a switch to the next bank if the OUT endpoint is composed of multiple banks.
RXOUTI should always be cleared before clearing FIFOCON to avoid missing an RXOUTI
event.
Figure 17-12. Example of an OUT endpoint with one data bank
OUT
RXOUTI
DATA
(bank 0)
ACK
NAK
HW
SW
OUT
DATA
(bank 0)
ACK
HW
SW
FIFOCON
read data from CPU
SW
BANK 0
read data from CPU
BANK 0
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