SAM4L Datasheet, PDF (660/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
26.5 I/O Lines Description
Table 26-1. I/O Lines Description
Pin Name
MISO
MOSI
SPCK
NPCS1-NPCS3
NPCS0/NSS
Pin Description
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select/Slave Select
Master
Input
Output
Output
Output
Output
Type
Slave
Output
Input
Input
Unused
Input
26.6 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
26.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.
The user must first configure the I/O Controller to assign the SPI pins to their peripheral
functions.
26.6.2 Clocks
The clock for the SPI bus interface (CLK_SPI) is generated by the Power Manager. This clock is
disabled at reset, and can be enabled in the Power Manager. It is recommended to disable the
SPI before disabling the clock, to avoid freezing the SPI in an undefined state.
26.6.3 Interrupts
The SPI interrupt request line is connected to the NVIC. Using the SPI interrupt requires the
NVIC to be programmed first.
26.7 Functional Description
26.7.1
Modes of Operation
The SPI operates in master mode or in slave mode.
Operation in master mode is configured by writing a one to the Master/Slave Mode bit in the
Mode Register (MR.MSTR). The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK
pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output
by the transmitter.
If the MR.MSTR bit is written to zero, the SPI operates in slave mode. The MISO line is driven by
the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the
transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a
Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other
purposes.
The data transfers are identically programmable for both modes of operations. The baud rate
generator is activated only in master mode.
42023C–SAM–02/2013
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