SAM4L Datasheet, PDF (668/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

Figure 26-8. Peripheral Deselection
CSAAT = 0 and CSNAAT = 0
TDRE
NPCS[0..3]
Write TDR
DLYBCT
A
A
DLYBCS
PCS = A
TDRE
NPCS[0..3]
Write TDR
DLYBCT
A
A
DLYBCS
PCS=A
TDRE
DLYBCT
NPCS[0..3]
A
B
DLYBCS
PCS = B
Write TDR
ATSAM4L4/L2
CSAAT = 1 and CSNAAT= 0 / 1
DLYBCT
A
A
A
DLYBCS
PCS = A
DLYBCT
A
A
A
DLYBCS
PCS = A
DLYBCT
A
B
DLYBCS
PCS = B
TDRE
CSAAT = 0 and CSNAAT = 0
DLYBCT
CSAAT = 0 and CSNAAT = 1
DLYBCT
NPCS[0..3]
A
A
PCS = A
Write TDR
A
A
DLYBCS
PCS = A
Figure 26-8 on page 668 shows different peripheral deselection cases and the effect of the
CSRn.CSAAT and CSRn.CSNAAT bits.
26.7.3.9
Mode Fault Detection
The SPI is capable of detecting a mode fault when it is configured in master mode and NPCS0,
MOSI, MISO, and SPCK are configured as open drain through the I/O Controller with either
internal or external pullup resistors. If the I/O Controller does not have open-drain capability,
mode fault detection must be disabled by writing a one to the Mode Fault Detection bit in the MR
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