SAM4L Datasheet, PDF (677/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

26.8.5 Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x10
Reset Value:
0x00000000
ATSAM4L4/L2
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
SPIENS
15
14
13
12
11
10
9
8
-
-
-
-
-
UNDES
TXEMPTY
NSSR
7
6
5
4
3
2
1
0
-
-
-
-
OVRES
MODF
TDRE
RDRF
• SPIENS: SPI Enable Status
1: This bit is set when the SPI is enabled.
0: This bit is cleared when the SPI is disabled.
• UNDES: Underrun Error Status (Slave Mode Only)
1: This bit is set when a transfer begins whereas no data has been loaded in the TDR register.
0: This bit is cleared when the SR register is read.
• TXEMPTY: Transmission Registers Empty
1: This bit is set when TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the
completion of such delay.
0: This bit is cleared as soon as data is written in TDR.
• NSSR: NSS Rising
1: A rising edge occurred on NSS pin since last read.
0: This bit is cleared when the SR register is read.
• OVRES: Overrun Error Status
1: This bit is set when an overrun has occurred. An overrun occurs when RDR is loaded at least twice from the serializer since
the last read of the RDR.
0: This bit is cleared when the SR register is read.
• MODF: Mode Fault Error
1: This bit is set when a Mode Fault occurred.
0: This bit is cleared when the SR register is read.
• TDRE: Transmit Data Register Empty
1: This bit is set when the last data written in the TDR register has been transferred to the serializer.
0: This bit is cleared when data has been written to TDR and not yet transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• RDRF: Receive Data Register Full
1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR.
0: No data has been received since the last read of RDR
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