SAM4L Datasheet, PDF (537/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
23.6.1 Basic Operation
23.6.1.1
Module Configuration
The GPIO user interface registers are organized into ports and each port controls 32 different
GPIO pins. Most of the registers supports bit wise access operations such as set, clear and tog-
gle in addition to the standard word access. For details regarding interface registers, refer to
Section 23.7.
23.6.1.2
Available Features
The GPIO features implemented are device dependent, and not all functions are implemented
on all pins. The user must refer to the Module Configuration section and the GPIO Function Mul-
tiplexing section in the Package and Pinout chapter for the device specific settings used in the
ATSAM4L4/L2.
Device specific settings includes:
• Number of GPIO pins
• Functions implemented on each pin
• Peripheral function(s) multiplexed on each GPIO pin
• Reset state of registers
23.6.1.3 Inputs
The level on each GPIO pin can be read through the Pin Value Register (PVR). This register
indicates the level of the GPIO pins regardless of the pins being driven by the GPIO or by an
external component. Note that due to power saving measures, the PVR register will only be
updated when the corresponding bit in GPER is one or if an interrupt is enabled for the pin, i.e.
IER is one for the corresponding pin.
23.6.1.4
Output Control
When the GPIO pin is assigned to a peripheral function, i.e. the corresponding bit in GPER is
zero, the peripheral determines whether the pin is driven or not.
When the GPIO pin is controlled by the GPIO, the value of Output Driver Enable Register
(ODER) determines whether the pin is driven or not. When a bit in this register is one, the corre-
sponding GPIO pin is driven by the GPIO. When the bit is zero, the GPIO does not drive the pin.
The level driven on a GPIO pin can be determined by writing the value to the corresponding bit
in the Output Value Register (OVR).
23.6.1.5
Peripheral Muxing
The GPIO allows a single GPIO pin to be shared by multiple peripheral pins and the GPIO itself.
Peripheral pins sharing the same GPIO pin are arranged into peripheral functions that can be
selected one at a time. Peripheral functions are configured by writing the selected function value
to the Peripheral Mux Registers (PMRn). To allow a peripheral pin access to the shared GPIO
pin, GPIO control must be disabled for that pin, i.e. the corresponding bit in GPER must read
zero.
A peripheral function value is set by writing bit zero to PMR0 and bit one to the same index posi-
tion in PMR1 and so on. In a system with 4 peripheral functions A,B,C, and D, peripheral
function C for GPIO pin four is selected by writing a zero to bit four in PMR0 and a one to the
same bit index in PMR1. Refer to the GPIO Function Multiplexing chapter for details regarding
pin function configuration for each GPIO pin.
42023C–SAM–02/2013
537