SAM4L Datasheet, PDF (395/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

17.7.2.14 Endpoint n Control Register
Register Name:
UECONn, n in [0..7]
Access Type:
Read-Only
Offset:
0x01C0 + (n * 0x04)
Reset Value:
0x00000000
ATSAM4L4/L2
31
30
29
28
27
26
25
24
-
-
-
-
-
-
BUSY1E
BUSY0E
23
22
21
20
19
18
17
16
-
-
-
-
STALLRQ
RSTDT
-
-
15
14
13
12
11
10
-
FIFOCON
KILLBK
NBUSYBKE RAMACERE
-
9
8
-
NREPLY
7
6
5
-
STALLEDE/
CRCERRE
-
4
NAKINE
3
NAKOUTE
2
RXSTPE/
ERRORFE
1
RXOUTE
0
TXINE
• BUSY0E: Busy Bank0 Enable
This bit is cleared when the BUSY0C bit is written to one.
This bit is set when the BUSY0ES bit is written to one. This will set the bank 0 as “busy”. All transactions, except SETUP,
destined to this bank will be rejected (i.e: NAK token will be answered).
• BUSY1E: Busy Bank1 Enable
This bit is cleared when the BUSY1C bit is written to one.
This bit is set when the BUSY1ES bit is written to one. This will set the bank 1 as “busy”. All transactions, except SETUP,
destined to this bank will be rejected (i.e: NAK token will be answered).
• STALLRQ: STALL Request
This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.
This bit is set when the STALLRQS bit is written to one, requesting a STALL handshake to be sent to the host.
• RSTDT: Reset Data Toggle
The data toggle sequence is cleared when the RSTDTS bit is written to one (i.e., Data0 data toggle sequence will be selected
for the next sent (IN endpoints) or received (OUT endpoints) packet.
This bit is always read as zero.
• FIFOCON: FIFO Control
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them for these endpoints. When read,
their value is always 0.
For IN endpoints:
This bit is cleared when the FIFOCONC bit is written to one, sending the FIFO data and switching to the next bank.
This bit is set simultaneously to TXINI, when the current bank is free.
For OUT endpoints:
This bit is cleared when the FIFOCONC bit is written to one, freeing the current bank and switching to the next.
This bit is set simultaneously to RXINI, when the current bank is full.
42023C–SAM–02/2013
395